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this document describes part-number-specific changes to recommended operating conditions and revised electrical specifications, as applicable, from those described in the general mpc8245 integrated processor hardware specifications (order no. mpc8245ec/d). the mpc8245 combines a powerpc? mpc603e core with a pci bridge. specifications that this document provides supersede those in the mpc8245 integrated processor hardware specifications , rev. 3 or later, for the part numbers listed in table a only. specifications that are not addressed in this document are unchanged. because this document is frequently updated, refer to http://www.motorola.com/semiconductors or to your motorola sales office for the latest version. note that headings and table numbers in this document are not consecutively numbered. they are intended to correspond to the heading or table in the general hardware specification that is affected. part numbers addressed in this document are listed in table a. for more detailed ordering information, see section 1.9, ?ordering information.? table a. part numbers addressed in this data sheet motorola part no. operating conditions significant differences from hardware specification processor version register value cpu frequency (mhz) v dd t j (c) mpc8245rzu400d 400 2.1 100 mv 0 to 85 modified voltage and temperature specifications to achieve 400 mhz 0x80811014 advance information MPC8245ARZUPNS rev. 1.0, 11/2003 mpc8245 part number specification for the mpc8245arzunnnx series motorola part numbers affected: mpc8245rzu400d mpc8245arzu400d mpc8245arzu466d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
2 mpc8245 part number specification for the mpc8245arzunnnx series motorola features features 1.2 features this section summarizes changes to the power management feature of the mpc8245 that the mpc8245 integrated processor hardware specifications describes. 1.3 general parameters this section summarizes changes to the general parameters of the mpc8245 core power supply that the mpc8245 integrated processor hardware specifications describes. 1.4.1.1 absolute maximum ratings the tables in this section describe the mpc8245 dc electrical characteristics. table 1 provides the absolute maximum ratings. mpc8245arzu400d 400 2.1 100 mv 0 to 85 modified voltage and temperature specifications to achieve 400 mhz 0x80811014 mpc8245arzu466d 466 2.1 100 mv 0 to 85 modified voltage and temperature specifications to achieve 466 mhz note: the x prefix in a motorola part number designates a pilot production prototype as defined by motorola sop 3-13. these are from a limited production volume of prototypes that are manufactured, tested, and inspected for quality on a qualified technology to simulate normal production. these parts have only preliminary reliability and characterization data. before pilot production prototypes can be shipped, written authorization from the customer must be on file in the applicable sales office to acknowledge the qualification status and the fact that product changes may still occur while shipping pilot production prototypes. the ?a? in the part number represents parts that are manufactured under a 29-angstrom process instead of the original 35-angstrom process. table 1. absolute maximum ratings characteristic 1 symbol range unit supply voltage?cpu core and peripheral logic v dd ?0.3 to 2.2 v supply voltage?memory bus drivers gv dd ?0.3 to 3.6 v supply voltage?pci and standard i/o buffers ov dd ?0.3 to 3.6 v supply voltage?plls av dd /av dd 2 ?0.3 to 2.2 v supply voltage?pci reference lv dd ?0.3 to 5.4 v table a. part numbers addressed in this data sheet (continued) motorola part no. operating conditions significant differences from hardware specification processor version register value cpu frequency (mhz) v dd t j (c) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mpc8245 part number specification for the mpc8245arzunnnx series 3 general parameters 1.4.1.2 dc electrical characteristics table 2 provides recommended operating conditions for mpc8245 part numbers that this document describes. 1.4.1.5 power characteristics the ac electrical characteristics and ac timing for the parts described in this document are unaffected, and comply with the mpc8245 integrated processor hardware specifications . table 5 provides the power consumption for the mpc8245 part numbers that this document describes. input voltage 2 v in ?0.3 to 3.6 v operational die-junction temperature range t j 0 to 105 c storage temperature range t stg ?55 to 150 c notes: 1. table 2 shows functional and tested operating conditions. absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. pci inputs with lv dd = 5 v 5% v dc may undergo corresponding stress at voltages exceeding lv dd + 0.5 v dc. table 2. recommended operating conditions 1 1 motorola tested these operating conditions and recommends them. proper device operation outside of these conditions is not guaranteed. characteristic symbol recommended value for 400 mhz cpu unit supply voltage v dd 2.1 v 100 mv v cpu pll supply voltage av dd 2.1 v 100 mv v pll supply voltage?peripheral logic av dd 2 2.1 v 100 mv v die-junction temperature 2 2 for information about the thermal characteristics of this part, refer to the mpc8245 integrated processor hardware specifications . note that the lower die-junction temperature creates a greater need to use a heat sink with this part. t j 0 to 85 c table 5. power consumption mode pci bus clock/memory bus clock cpu clock frequency (mhz) unit notes 66133/399 66133/466 typical 2.8 3.2 w 1, 5 max?cfp 3.3 3.6 w 1, 2 max?int 2.8 3.1 w 1, 3 doze 1.9 2.1 w 1, 4, 6 table 1. absolute maximum ratings (continued) characteristic 1 symbol range unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
4 mpc8245 part number specification for the mpc8245arzunnnx series motorola general parameters general parameters 1.4.1.2 output ac timing specification table 11 provides the processor bus ac timing specification for output hold time for debug signals in the 466-mhz cpu of the mpc8245 at recommended operating conditions (see table 2) with lv dd = 3.3 v 0.3 v. all output timings assume a purely resistive 50- ? load (see figure 14 in the mpc8245 integrated processor hardware specification ). output timings are measured at the pin; time-of-flight delays must be added for trace lengths, vias, and connectors in the system. these specifications are for the default driver strengths listed in the mpc8245 integrated processor hardware specifications . nap 0.7 0.8 w 1, 4, 6 sleep 0.4 0.4 w 1, 4, 6 i/o power supplies 10 mode range range unit notes typ?ov dd 140?360 140?360 mw 7, 8 typ?gv dd 340?920 340?930 mw 7, 9 notes: 1. the values include v dd , av dd , and av dd 2, but do not include i/o supply power. 2. maximum?fp power is measured at v dd = 2.1 v with dynamic power management enabled while running an entirely cache-resident, looping, floating point multiplication instruction. 3. maximum?int power is measured at v dd = 2.1 v with dynamic power management enabled while running entirely cache-resident, looping, integer instructions. 4. power saving mode maximums are measured at v dd = 2.1 v while the device is in doze, nap, or sleep mode. 5. typical power is measured at v dd = av dd = 2.1 v, ov dd = 3.3 v where a nominal fp value, a nominal int value, and a value where there is a continuous flush of cache lines with alternating ones, and zeros on 64-bit boundaries to local memory are averaged. 6. power saving mode data measured with only two pci_clks and two sdram_clks enabled. 7. the typical minimum i/o power values was the result of the mpc8245 performing cache resident integer operations at the slowest frequency combination of 33:66:200 (pci:mem:cpu) mhz. 8. the typical maximum ov dd value resulted from the mpc8245 operating at the fastest frequency combination of 66:133:399 (pci:mem:cpu) mhz for the 400-mhz part, 66:133:466 (pci:mem:cpu) mhz for the 466-mhz part, and performing continuous flushes of cache lines with alternating ones and zeros to pci memory. 9. the typical maximum gv dd value resulted from the mpc8245 operating at the fastest frequency combination of 66:133:399 (pci:mem:cpu) mhz for the 400-mhz part, 66:133:466 (pci:mem:cpu) mhz for the 466-mhz part, and performing continuous flushes of cache lines with alternating ones and zeros on 64-bit boundaries to local memory. 10. power consumption of pll supply pins (av dd and av dd 2) < 15 mw that the design guarantees but were not tested. table 5. power consumption (continued) mode pci bus clock/memory bus clock cpu clock frequency (mhz) unit notes 66133/399 66133/466 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mpc8245 part number specification for the mpc8245arzunnnx series 5 general parameters table 11. output ac timing specifications num characteristic min max unit notes 13b output hold (debug signals) 0.0 ? ns 1 note: 1. all memory and related interface output signal specifications are specified from the vm = 1.4 v of the rising edge of the memory bus clock, sdram_sync_in to the ttl level (0.8 or 2.0 v) of the signal in question. sdram_sync_in is the same as pci_sync_in in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising edges occur on every rising and falling edge of pci_sync_in). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
6 mpc8245 part number specification for the mpc8245arzunnnx series motorola pll configuration pll configuration 1.6 pll configuration the mpc8245 internal plls are configured by the pll_cfg[0:4] signals. for a given pci_sync_in (pci bus) frequency, the pll configuration signals set both the peripheral logic/memory bus pll (vco) frequency of operation for the pci-to-memory frequency multiplying and the mpc603e cpu pll (vco) frequency of operation for memory-to-cpu frequency multiplying. the pll configurations for the 400- and 466-mhz parts are shown in table 17 and table 18, respectively. table 17. pll configurations for the 400-mhz part offering ref pll_cfg[0:4] 11,14,15 400-mhz part 9 multipliers pci clock input (pci_sync_in) range 1 (mhz) periph logic/mem bus clock range (mhz) cpu clock range (mhz) pci-to-mem (mem vco) mem-to-cpu (cpu vco) 0 00000 25?44 2 75?132 188?330 3 (2) 2.5 (2) 1 00001 25?44 5 75?132 225?396 3 (2) 3 (2) 2 00010 13 50 9 ?66 1 50?66 225?297 1 (4) 4.5 (2) 3 00011 16 50 8 ?66 1 50?66 100?133 1 (bypass) 2 (4) 4 00100 25?46 4 50?92 100?184 2 (4) 2 (4) 6 00110 17 bypass bypass bypass 7 (rev. b) 00111 60 6 ?66 1 60?66 180?198 1 (bypass) 3 (2) 7 (rev. d) 00111 13 25?28 5 100?112 350?392 4(2) 3.5(2) 8 01000 60 6 ?66 1 60?66 180?198 1 (4) 3 (2) 9 01001 45 6 ?66 1 90?132 180?264 2 (2) 2 (2) a 01010 25?44 5 50?88 225?396 2 (4) 4.5 (2) b 01011 45 3 ?66 1 68?99 204?297 1.5 (2) 3 (2) c 01100 36 6 ?46 4 72?92 180?230 2 (4) 2.5 (2) d 01101 45 3 ?66 1 68?99 238?347 1.5 (2) 3.5 (2) e 01110 30 6 ?46 4 60?92 180?276 2 (4) 3 (2) f 01111 25?38 5 75?114 263?399 3(2) 3.5(2) 10 10000 30?44 2 60?132 180?264 3 (2) 2 (2) 11 10001 25?33 2 100?132 250?330 4(2) 2.5(2) 12 10010 60 6 ?66 1 90?99 180?198 1.5 (2) 2 (2) 13 10011 25?33 5 100?132 300?396 4(2) 3(2) 14 10100 26 6 ?47 4 52?94 182?329 2 (4) 3.5 (2) 15 10101 27 3 ?40 5 68?100 272?400 2.5 (2) 4 (2) 16 10110 25?46 4 50?92 200?368 2 (4) 4 (2) 17 10111 25?33 2 100?132 200?264 4 (2) 2 (2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mpc8245 part number specification for the mpc8245arzunnnx series 7 pll configuration 18 11000 27 3 ?53 5 68?132 204?396 2.5 (2) 3 (2) 19 11001 36 6 ?66 1 72?132 180?330 2 (2) 2.5 (2) 1a 11010 50 9 ?66 1 50?66 200?264 1 (4) 4 (2) 1b 11011 13 34 3 ?66 1 68?132 204?396 2 (2) 3 (2) 1c 11100 44 6 ?66 1 66?99 198?297 1.5 (2) 3 (2) 1d 11101 48 6 ?66 1 72?99 180?248 1.5 (2) 2.5(2) 1e (rev. b) 11110 10 not usable off off 1e (rev. d) 11110 33 3 ?57 5 66?114 231?399 2(2) 3.5(2) 1f 11111 10 not usable off off notes: 1. limited by maximum pci input frequency (66 mhz) 2. limited by maximum system memory interface operating frequency (133 mhz) 3. limited by minimum memory vco frequency (132 mhz) 4. limited due to maximum memory vco frequency (372 mhz) 5. limited by maximum cpu operating frequency (400 mhz) 6. limited by minimum cpu vco frequency (360 mhz) 7. limited by maximum cpu vco frequency (800 mhz) 8. limited by minimum cpu operating frequency (100 mhz) 9. limited by minimum memory bus frequency (50 mhz) 10.in clock off mode, no clocking occurs inside the mpc8245, regardless of the pci_sync_in input. 11.range values are shown rounded down to the nearest whole number (decimal place accuracy removed) for clarity. 12.pll_cfg[0:4] settings that are not listed are reserved. 13.multiplier ratios for this pll_cfg[0:4] setting are different from the mpc8240 and are not backwards-compatible. 14.pci_sync_in range for this pll_cfg[0:4] setting is different from the mpc8240 and may not be fully backwards-compatible. 15.bits 7? 4 of register offset <0xe2> contain the pll_cfg[0:4] setting value. 16.in pll bypass mode, the pci_sync_in input signal clocks the internal processor directly, the peripheral logic pll is disabled, and the bus mode is set for 1:1 (pci:mem) mode operation. this mode is intended for hardware modeling support. the ac timing specifications given in this document do not apply in the pll bypass mode. 17.in dual pll bypass mode, the pci_sync_in input signal clocks the internal peripheral logic directly, the peripheral logic pll is disabled, and the bus mode is set for 1:1 (pci_sync_in:mem) mode operation. in this mode, the osc_in input signal clocks the internal processor directly in 1:1 (osc_in:cpu) mode operation, and the processor pll is disabled. the pci_sync_in and osc_in input clocks must be externally synchronized. this mode is intended for hardware modeling support. the ac timing specifications given in this document do not apply in the dual pll bypass mode. table 17. pll configurations for the 400-mhz part offering (continued) ref pll_cfg[0:4] 11,14,15 400-mhz part 9 multipliers pci clock input (pci_sync_in) range 1 (mhz) periph logic/mem bus clock range (mhz) cpu clock range (mhz) pci-to-mem (mem vco) mem-to-cpu (cpu vco) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
8 mpc8245 part number specification for the mpc8245arzunnnx series motorola pll configuration pll configuration table 18. pll configurations for the 466-mhz part offering ref pll_cfg[0:4] 11,14,15 466-mhz part 9 multipliers pci clock input (pci_sync_in) range 1 (mhz) periph logic/mem bus clock range (mhz) cpu clock range (mhz) pci-to-mem (mem vco) mem-to-cpu (cpu vco) 0 00000 25?44 2 75?132 188?330 3 (2) 2.5 (2) 1 00001 25?44 2 75?132 225?396 3 (2) 3 (2) 2 00010 13 50 9 ?66 1 50?66 225?297 1 (4) 4.5 (2) 3 00011 16 50 8 ?66 1 50?66 100?133 1(bypass) 2 (4) 4 00100 25?46 4 50?92 100?184 2 (4) 2 (4) 6 00110 17 bypass bypass bypass 7 00111 25?33 2 100?133 350?466 4(2) 3.5(2) 8 01000 60 6 ?66 1 60?66 180?198 1 (4) 3 (2) 9 01001 45 6 ?66 1 90?132 180?264 2 (2) 2 (2) a 01010 25?46 4 50?96 225?432 2 (4) 4.5 (2) b 01011 45 3 ?66 1 68?99 204?297 1.5 (2) 3 (2) c 01100 36 6 ?46 4 72?92 180?230 2 (4) 2.5 (2) d 01101 45 3 ?66 1 68?99 238?347 1.5 (2) 3.5 (2) e 01110 30 6 ?46 4 60?92 180?276 2 (4) 3 (2) f 01111 25?44 2 75?132 263?462 3(2) 3.5(2) 10 10000 30 6 ?44 2 60?132 180?264 3 (2) 2 (2) 11 10001 25?33 2 100?132 250?330 4(2) 2.5(2) 12 10010 60 6 ?66 1 90?99 180?198 1.5 (2) 2 (2) 13 10011 25?33 2 100?132 300?396 4(2) 3(2) 14 10100 26 6 ?47 4 52?94 182?329 2 (4) 3.5 (2) 15 10101 27 3 ?46 5 68?115 272?460 2.5 (2) 4 (2) 16 10110 25?46 4 50?92 200?368 2 (4) 4 (2) 17 10111 25?33 2 100?132 200?264 4 (2) 2 (2) 18 11000 27 3 ?53 2 68?132 204?396 2.5 (2) 3 (2) 19 11001 36 6 ?66 1 72?132 180?330 2 (2) 2.5 (2) 1a 11010 50 9 ?66 1 50?66 200?264 1 (4) 4 (2) 1b 11011 13 34 3 ?66 1 68?132 204?396 2 (2) 3 (2) 1c 11100 44 6 ?66 1 66?99 198?297 1.5 (2) 3 (2) 1d 11101 48 6 ?66 1 72?99 180?248 1.5 (2) 2.5(2) 1e 11110 33 3 ?66 1,2 66?132 231?462 2(2) 3.5(2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mpc8245 part number specification for the mpc8245arzunnnx series 9 pll configuration 1f 11111 10 not usable off off notes: 1. limited by maximum pci input frequency (66 mhz) 2. limited by maximum memory interface operating frequency (133 mhz) 3. limited by minimum memory vco frequency (132 mhz) 4. limited due to maximum memory vco frequency (372 mhz) 5. limited by maximum cpu operating frequency (466 mhz) 6. limited by minimum cpu vco frequency (360 mhz) 7. limited by maximum cpu vco frequency (932 mhz) 8. limited by minimum cpu operating frequency (100 mhz) 9. limited by minimum memory bus frequency (50 mhz) 10.in clock off mode, no clocking occurs inside the mpc8245 regardless of the pci_sync_in input. 11.range values are shown rounded down to the nearest whole number (decimal place accuracy removed) for clarity. 12.pll_cfg[0:4] settings not listed are reserved. 13.multiplier ratios for this pll_cfg[0:4] setting are different from the mpc8240 and are not backwards-compatible. 14.pci_sync_in range for this pll_cfg[0:4] setting is different from the mpc8240 and may not be fully backwards-compatible. 15.bits 7?4 of register offset <0xe2> contain the pll_cfg[0:4] setting value. 16.in pll bypass mode, the pci_sync_in input signal clocks the internal processor directly, the peripheral logic pll is disabled, and the bus mode is set for 1:1 (pci:mem) mode operation. this mode is intended for hardware modeling support. the ac timing specifications given in this document do not apply in the pll bypass mode. 17.in dual pll bypass mode, the pci_sync_in input signal clocks the internal peripheral logic directly, the peripheral logic pll is disabled, and the bus mode is set for 1:1 (pci_sync_in:mem) mode operation. in this mode, the osc_in input signal clocks the internal processor directly in 1:1 (osc_in:cpu) mode operation, and the processor pll is disabled. the pci_sync_in and osc_in input clocks must be externally synchronized. this mode is intended for hardware modeling support. the ac timing specifications given in this document do not apply in the dual pll bypass mode. table 18. pll configurations for the 466-mhz part offering (continued) ref pll_cfg[0:4] 11,14,15 466-mhz part 9 multipliers pci clock input (pci_sync_in) range 1 (mhz) periph logic/mem bus clock range (mhz) cpu clock range (mhz) pci-to-mem (mem vco) mem-to-cpu (cpu vco) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
10 mpc8245 part number specification for the mpc8245arzunnnx series motorola ordering information ordering information 1.9 ordering information ordering information for the parts that this document covers fully is provided in section 1.9.1, ?part numbers fully addressed by this document.? section 1.9.2, ?part marking,? addresses the marking specifications. 1.9.1 part numbers fully addressed by this document table 20 shows the ordering information for the mpc8245 parts that this document describes. note that the individual part numbers correspond to a maximum processor core frequency. 1.9.2 part marking figure 31 shows how parts are marked. figure 31. motorola part marking for tbga device table 20. part numbering nomenclature mpc nnnn x 1 1 note that on the standard ?l? specification, the process descriptor is not added because it is the standard size for the part (35 angstrom). the 400- and 466-mhz parts marked with ?a? follow a different process description (29 angstrom), which is different from the 35-angstrom process on the 400 mhz non-a process parts. r xx nnn x product code part identifier process descriptor part specification package processor frequency (mhz) revision level mpc 8245 - r = partial spec. 2.1 v 100 mv 0 to 85 c zu = tbga 400 contact local motorola sales office mpc 8245 a = 29 angstrom r = partial spec. 2.1 v 100 mv 0 to 85 c zu = tbga 400, 466 contact local motorola sales office notes : mmmmmm is the 6-digit mask number. atwlyywwa is the traceability code. mpc8245ar zunnnx mmmmmm atwlyywwa 8245 tbga f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola mpc8245 part number specification for the mpc8245arzunnnx series 11 document revision history document revision history table b provides a revision history for this part number specification. table b document revision history rev. no. substantive change(s) 0 original release 0.1 minor edit to part number 1.0 added to list of parts covered by this document, including the non ?a? process identifier parts. updated table a and table 20. nontechnical reformatting f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
MPC8245ARZUPNS how to reach us: usa/europe/locations not listed: motorola literature distribution p.o. box 5405, denver, colorado 80217 1-480-768-2130 (800) 521-6274 japan: motorola japan ltd. sps, technical information center 3-20-1, minami-azabu minato-ku tokyo 106-8573 japan 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd. silicon harbour centre, 2 dai king street tai po industrial estate, tai po, n.t., hong kong 852-26668334 technical information center: (800) 521-6274 home page: www.motorola.com/semiconductors information in this document is provided solely to enable system and software implementers to use motorola products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and the stylized m logo are registered in the u.s. patent and trademark office. digital dna is a trademark of motorola, inc. the described product contains a powerpc processor core. the powerpc name is a trademark of ibm corp. and used under license. all other product or service names are the property of their re spective owners. motorola, inc. is an equal opportunity/affirmative action employer. ? motorola, inc. 2003 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

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